SDA9220-5 Datasheet, PDF (24/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
Characteristics (cont’d)
Parameter
Symbol
Limit Values
min. typ.
max.
Unit Test Condition
Output Clock LL1.5X/Reference Clock: LLIN (refer to figure 9a)
Period
H-pulse width
L-pulse width
Clock skew *⁾
Load capacitance
H-output voltage
L-output voltage
T_LL1.5X
34
37
t_WH
12
t_WL
12
t_SK
0
C_L
V_QH
2.4
V_QL
40
ns
ns
ns
15
ns
50
pF
V
0.4
V
I_QH = – 2.5 mA
I_QL = 5 mA
Output Clock LL3X/Reference Clock: LLIN (refer to figure 9a)
Period
H-pulse width
L-pulse width
Clock skew *⁾
Load capacitance
H-output voltage
L-output voltage
T_LL3X
68
74
t_WH
25
t_WL
25
t_SK
0
C_L
V_QH
2.4
V_QL
80
ns
ns
ns
15
ns
50
pF
V
0.4
V
*) With steady-state PLL.
I_QH = – 2.5 mA
I_QL = 5 mA
Semiconductor Group
140