SDA9220-5 Datasheet, PDF (42/42 Pages) Siemens Semiconductor Group – Memory Sync Controller III

SDA 9220-5
Figure 22
Timing for I²C Bus
Parameter
Symbol
Clock frequency
Inactive time before start of new transmission
Hold time for start condition
(after this time first clock pulse is generated)
f_SCL
t_BUF
t_{HD; STA}
Low clock phase
t_LOW
High clock phase
t_HIGH
Setup time for data
t_{SU; DAT}
Rise time for SDA and SCL signals
t_TLH
Fall time for SDA and SCL signals
t_THL
Setup time for SCL clock in stop condition
t_{SU; STO}
All values are referred to specified input levels V_IH and V_IL.
Limit Values Unit
min.
max.
0
100
kHz
4.7
µs
4.0
µs
4.7
µs
4.0
µs
250
ns
1
µs
300
ns
4.7
µs
Semiconductor Group
158