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| K4B1G0446G Datasheet, PDF (63/64 Pages) Samsung semiconductor – 1Gb G-die DDR3 SDRAM | |||
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K4B1G0446G
K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIS
tIH
CK
CK
DQS
tIS tIH
DQS
VDDQ
tDS tDH
nominal
line
VIH(AC) min
VREF to ac
region
VIH(DC) min
VREF(DC)
tangent
line
tDS tDH
tVAC
tangent
line
VIL(DC) max
VIL(AC) max
nominal
line
VSS
â TF
VREF to ac
region
tVAC
â TR
Setup Slew Rate
Rising Signal
=
tangent line[VIH(AC)min - VREF(DC)]
â TR
Setup Slew Rate
Falling Signal =
tangent line[VREF(DC) - VIL(AC)max]
â TF
Figure 27. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
- 63 -
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