K4B1G0446G Datasheet, PDF (3/64 Pages) Samsung semiconductor – 1Gb G-die DDR3 SDRAM

K4B1G0446G
K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
Table Of Contents
1Gb G-die DDR3 SDRAM
1. Ordering Information ..................................................................................................................................................... 5
2. Key Features................................................................................................................................................................. 5
3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6
3.1 x4 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 6
3.2 x8 Package Pinout (Top view) : 78ball FBGA Package .......................................................................................... 7
3.3 FBGA Package Dimension (x4/x8) .......................................................................................................................... 8
4. Input/Output Functional Description.............................................................................................................................. 9
5. DDR3 SDRAM Addressing ........................................................................................................................................... 10
6. Absolute Maximum Ratings .......................................................................................................................................... 11
6.1 Absolute Maximum DC Ratings............................................................................................................................... 11
6.2 DRAM Component Operating Temperature Range ................................................................................................ 11
7. AC & DC Operating Conditions..................................................................................................................................... 11
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 11
8. AC & DC Input Measurement Levels ............................................................................................................................ 12
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 12
8.2 V_REF Tolerances...................................................................................................................................................... 13
8.3 AC & DC Logic Input Levels for Differential Signals ............................................................................................... 14
8.3.1. Differential signals definition ............................................................................................................................ 14
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 14
8.3.3. Single-ended requirements for differential signals ........................................................................................... 15
8.4 Differential Input Cross Point Voltage...................................................................................................................... 16
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 16
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 16
9. AC & DC Output Measurement Levels ......................................................................................................................... 17
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 17
9.2 Differential AC & DC Output Levels......................................................................................................................... 17
9.3 Single-ended Output Slew Rate .............................................................................................................................. 17
9.4 Differential Output Slew Rate .................................................................................................................................. 18
9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 18
9.6 Overshoot/Undershoot Specification ....................................................................................................................... 19
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 19
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 19
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 20
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 21
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 21
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 22
9.8.2. ODT Temperature and Voltage sensitivity ...................................................................................................... 23
9.9 ODT Timing Definitions ........................................................................................................................................... 24
9.9.1. Test Load for ODT Timings .............................................................................................................................. 24
9.9.2. ODT Timing Definitions .................................................................................................................................... 24
10. IDD Current Measure Method..................................................................................................................................... 27
10.1 IDD Measurement Conditions ............................................................................................................................... 27
11. 1Gb DDR3 SDRAM G-die IDD Specification Table .................................................................................................... 36
12. Input/Output Capacitance ........................................................................................................................................... 37
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-1866 ...................................................................... 38
13.1 Clock Specification ................................................................................................................................................ 38
13.1.1. Definition for tCK(avg).................................................................................................................................... 38
13.1.2. Definition for tCK(abs).................................................................................................................................... 38
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 38
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 38
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 38
13.1.6. Definition for tERR(nper) ................................................................................................................................ 38
13.2 Refresh Parameters by Device Density................................................................................................................. 39
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 39
13.3.1. Speed Bin Table Notes .................................................................................................................................. 43
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