K4B1G0446G Datasheet, PDF (47/64 Pages) Samsung semiconductor – 1Gb G-die DDR3 SDRAM

K4B1G0446G
K4B1G0846G
datasheet
Rev. 1.01
DDR3 SDRAM
[ Table 49 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866
Speed
DDR3-1600
DDR3-1866
Parameter
Symbol
MIN
MAX
MIN
MAX
Clock Timing
Minimum Clock Cycle Time (DLL off mode)
tCK(DLL_OFF)
8
-
8
-
Average Clock Period
tCK(avg)
See Speed Bins Table
Clock Period
tCK(abs) tCK(avg)min + tJIT(per)min
tCK(avg)max +
tJIT(per)max
tCK(avg)min +
tJIT(per)min
tCK(avg)max +
tJIT(per)max
Average high pulse width
tCH(avg)
0.47
0.53
0.47
0.53
Average low pulse width
tCL(avg)
0.47
0.53
0.47
0.53
Clock Period Jitter
tJIT(per)
-70
70
-60
60
Clock Period Jitter during DLL locking period
tJIT(per, lck)
-60
60
-50
50
Cycle to Cycle Period Jitter
tJIT(cc)
140
120
Cycle to Cycle Period Jitter during DLL locking period
tJIT(cc, lck)
120
100
Cumulative error across 2 cycles
tERR(2per)
-103
103
-88
88
Cumulative error across 3 cycles
tERR(3per)
-122
122
-105
105
Cumulative error across 4 cycles
tERR(4per)
-136
136
-117
117
Cumulative error across 5 cycles
tERR(5per)
-147
147
-126
126
Cumulative error across 6 cycles
tERR(6per)
-155
155
-133
133
Cumulative error across 7 cycles
tERR(7per)
-163
163
-139
139
Cumulative error across 8 cycles
tERR(8per)
-169
169
-145
145
Cumulative error across 9 cycles
tERR(9per)
-175
175
-150
150
Cumulative error across 10 cycles
tERR(10per)
-180
180
-154
154
Cumulative error across 11 cycles
tERR(11per)
-184
184
-158
158
Cumulative error across 12 cycles
tERR(12per)
-188
188
-161
161
Cumulative error across n = 13, 14 ... 49, 50 cycles
tERR(nper)
tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min
tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max
Absolute clock HIGH pulse width
tCH(abs)
0.43
-
0.43
-
Absolute clock Low pulse width
tCL(abs)
0.43
-
0.43
-
Data Timing
DQS,DQS to DQ skew, per group, per access
tDQSQ
-
100
-
85
DQ output hold time from DQS, DQS
tQH
0.38
-
0.38
-
DQ low-impedance time from CK, CK
tLZ(DQ)
-450
225
-390
195
DQ high-impedance time from CK, CK
tHZ(DQ)
-
225
-
195
Data setup time to DQS, DQS referenced to V_IH(AC)V_IL(AC) lev-
tDS(base)
AC150
10
-
-
-
els
tDS(base)
AC135
-
-
0
-
Data hold time to DQS, DQS referenced to V_IH(AC)V_IL(AC) levels
tDH(base)
DC100
45
-
20
-
DQ and DM Input pulse width for each input
tDIPW
360
-
320
-
Data Strobe Timing
DQS, DQS differential READ Preamble
tRPRE
0.9
NOTE 19
0.9
NOTE 19
DQS, DQS differential READ Postamble
tRPST
0.3
NOTE 11
0.3
NOTE 11
DQS, DQS differential output high time
tQSH
0.4
-
0.4
-
DQS, DQS differential output low time
tQSL
0.4
-
0.4
-
DQS, DQS differential WRITE Preamble
tWPRE
0.9
-
0.9
-
DQS, DQS differential WRITE Postamble
tWPST
0.3
-
0.3
-
DQS, DQS rising edge output access time from rising CK, CK
tDQSCK
-225
225
-195
195
DQS, DQS low-impedance time (Referenced from RL-1)
tLZ(DQS)
-450
225
-390
195
DQS, DQS high-impedance time (Referenced from RL+BL/2)
tHZ(DQS)
-
225
-
195
DQS, DQS differential input low pulse width
tDQSL
0.45
0.55
0.45
0.55
DQS, DQS differential input high pulse width
tDQSH
0.45
0.55
0.45
0.55
DQS, DQS rising edge to CK, CK rising edge
tDQSS
-0.27
0.27
-0.27
0.27
DQS,DQS falling edge setup time to CK, CK rising edge
tDSS
0.9
NOTE 19
0.18
-
DQS,DQS falling edge hold time to CK, CK rising edge
tDSH
0.3
NOTE 11
0.18
-
Units
NOTE
ns
6
ps
ps
tCK(avg)
tCK(avg)
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
24
tCK(avg)
25
tCK(avg)
26
ps
tCK(avg)
ps
ps
13
13, g
13,14, f
13,14, f
ps
d, 17
ps
d, 17
ps
d, 17
ps
28
tCK
tCK
tCK(avg)
tCK(avg)
tCK
tCK
ps
ps
ps
tCK
tCK
tCK(avg)
tCK(avg)
tCK(avg)
13, 19, g
11, 13, b
13, g
13, g
13,f
13,14,f
12,13,14
29, 31
30, 31
c
c, 32
c, 32
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