K4B4G0446B Datasheet, PDF (46/59 Pages) Samsung semiconductor – DDP 4Gb B-die DDR3 SDRAM Specification

K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
[ Table 47 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
Parameter
Symbol
MIN
MAX
Power Down Timing
Exit Power Down with DLL on to any valid com-
mand;Exit Percharge Power Down with DLL
frozen to commands not requiring a locked DLL
max
tXP
(3nCK,
-
7.5ns)
Exit Precharge Power Down with DLL frozen to com-
mands requiring a locked DLL
tXPDLL
max
(10nCK,
24ns)
-
CKE minimum pulse width
max
tCKE
(3nCK,
-
7.5ns)
Command pass disable delay
tCPDED
1
-
Power Down Entry to Exit Timing
tPD
tCKE(min) 9*tREFI
Timing of ACT command to Power Down entry
tACTPDEN
1
-
Timing of PRE command to Power Down entry
tPRPDEN
1
-
Timing of RD/RDA command to Power Down entry
tRDPDEN RL + 4 +1
-
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
WL + 4
tWRPDEN +(tWR/
-
tCK(avg))
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BL4OTF)
tWRAPDEN
WL + 4
+WR +1
-
Timing of WR command to Power Down entry
(BL4MRS)
WL + 2
tWRPDEN +(tWR/
-
tCK(avg))
Timing of WRA command to Power Down entry
(BL4MRS)
tWRAPDEN
WL +2 +WR
+1
-
Timing of REF command to Power Down entry
tREFPDEN
1
-
Timing of MRS command to Power Down entry
tMRSPDEN tMOD(min)
-
ODT Timing
ODT high time without write command or with wirte
command and BC4
ODTH4
4
-
ODT high time with Write command and BL8
ODTH8
6
-
Asynchronous RTT tum-on delay (Power-Down with
DLL frozen)
tAONPD
2
8.5
Asynchronous RTT tum-off delay (Power-Down with
DLL frozen)
tAOFPD
2
8.5
ODT turn-on
tAON
-400
400
RTT_NOM and RTT_WR turn-off time from ODTLoff
reference
tAOF
0.3
0.7
RTT dynamic change skew
tADC
0.3
0.7
Write Leveling Timing
First DQS pulse rising edge after tDQSS margining
mode is programmed
tWLMRD
40
-
DQS/DQS delay after tDQS margining mode is pro-
grammed
tWLDQSEN
25
-
Setup time for tDQSS latch
tWLS
325
-
Write leveling hold time from rising DQS, DQS cross-
ing to rising CK, CK crossing
tWLH
325
-
Write leveling output delay
tWLO
0
9
Write leveling output error
tWLOE
0
2
DDR3-1066
MIN
MAX
max
(3nCK,
7.5ns)
max
(10nCK,
24ns)
max
(3nCK,
5.625ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
-
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
2
8.5
2
8.5
-300
300
0.3
0.7
0.3
0.7
40
-
25
-
245
-
245
-
0
9
0
2
DDR3-1333
MIN
MAX
max
(3nCK,6ns)
-
max
(10nCK,
24ns)
max
(3nCK,
5.625ns)
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
-
-
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
2
8.5
2
8.5
-250
250
0.3
0.7
0.3
0.7
40
-
25
-
195
-
195
-
0
9
0
2
DDR3-1600
MIN
MAX
max
(3nCK,6ns)
-
max
(10nCK,
-
24ns)
max
(3nCK,5ns)
-
1
tCKE(min)
1
1
RL + 4 +1
WL + 4
+(tWR/
tCK(avg))
WL + 4
+WR +1
WL + 2
+(tWR/
tCK(avg))
WL +2 +WR
+1
1
tMOD(min)
-
9*tREFI
-
-
-
-
-
-
-
-
-
4
-
6
-
2
8.5
2
8.5
-225
225
0.3
0.7
0.3
0.7
40
-
25
-
165
-
165
-
0
7.5
0
2
Units
nCK
tCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ps
tCK(avg)
tCK(avg)
tCK
tCK
ps
ps
ns
ns
Note
2
15
20
20
9
10
9
10
20,21
7,f
8,f
f
3
3
Page 46 of 59
Rev. 1.0 March 2009