K4B4G0446B Datasheet, PDF (32/59 Pages) Samsung semiconductor – DDP 4Gb B-die DDR3 SDRAM Specification

K4B4G0446B
K4B4G0846B
[ Table 32 ] IDD0 Measurement - Loop Pattern¹
DDP 4Gb DDR3 SDRAM
0
0
ACT 0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D 1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D 1
1
1
1
0
0
00
0
0
0
0
-
...
repeat pattern 1...4 until nRAS - 1, truncate if necessary
nRAS
PRE 0
0
1
0
0
0
00
0
0
0
0
-
...
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC + 0
ACT 0
0
1
1
0
0
00
0
0
F
0
-
1*nRC + 1, 2
D, D 1
0
0
0
0
0
00
0
0
F
0
-
1*nRC + 3, 4
D, D 1
1
1
1
0
0
00
0
0
F
0
-
...
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
1*nRC + nRAS
PRE 0
0
1
0
0
0
00
0
0
F
0
...
repeat 1...4 until 2*nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
Note :
1. DM must be driben LOW all the time. DQS, DQS are MID-LEVEL.
2. DQ signals are MID-LEVEL.
Page 32 of 59
Rev. 1.0 March 2009