K4B4G0446B Datasheet, PDF (28/59 Pages) Samsung semiconductor – DDP 4Gb B-die DDR3 SDRAM Specification

K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
10.0 IDD Specification Parameters and Test Conditions
10.1 IDD Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and
IDDQ measurements.
- IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and
IDD7) are measured as time-averaged currents with all V_DD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in
IDD currents.
- IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all V_DDQ balls of the DDR3 SDRAM under test tied
together. Any IDD current is not included in IDDQ currents.
Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO
power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since V_DD and V_DDQ
are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply :
- "0" and "LOW" is defined as V_IN <= V_ILAC(max).
- "1" and "HIGH" is defined as V_IN >= V_IHAC(min).
- "FLOATING" is defined as inputs are V_REF = V_DD / 2.
- Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 30.
- Basic IDD and IDDQ Measurement Conditions are described in Table 31.
- Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 33 through Table 39.
- IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
- Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
- Define D = {CS, RAS, CAS, WE} := {HIGH, LOW, LOW, LOW}
- Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH}
Timing parameters are listed in the following table:
[ Table 30 ] Timing used for IDD and IDDQ Measured-Loop Patterns.
Parameter Bin
tCKmin(IDD)
CL(IDD)
tRCDmin(IDD)
tRCmin(IDD)
tRASmin(IDD)
tRPmin(IDD)
tFAW(IDD)
x4/x8
x16
tRRD(IDD)
x4/x8
x16
tRFC(IDD) - 512Mb
tRFC(IDD) - 1Gb
tRFC(IDD) - 2Gb
tRFC(IDD) - 4Gb
tRFC(IDD) - 8Gb
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Unit
5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9 10-10-10 8-8-8 9-9-9 10-10-10 11-11-11
2.5
1.875
1.5
1.25
ns
5
6
6
7
8
7
8
9
10
8
9
10
11
nCK
5
6
6
7
8
7
8
9
10
8
9
10
11
nCK
20
21
26
27
28
31
32
33
34
36
37
38
39
nCK
15
20
24
28
nCK
5
6
6
7
8
7
8
9
10
8
9
10
11
nCK
16
20
20
24
nCK
20
27
30
32
nCK
4
4
4
5
nCK
4
6
5
6
nCK
36
48
60
72
nCK
44
59
74
88
nCK
64
86
107
128
nCK
120
160
200
240
nCK
140
187
234
280
nCK
Page 28 of 59
Rev. 1.0 March 2009