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K4B4G0446B Datasheet, PDF (15/59 Pages) Samsung semiconductor – DDP 4Gb B-die DDR3 SDRAM Specification
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K4B4G0446B
K4B4G0846B
8.3 AC and DC Logic Input Levels for Ditterential Signals
8.3.1 Differential signal definition
VIH.DIFF.AC.MIN
tDVAC
VIH.DIFF.MIN
DDP 4Gb DDR3 SDRAM
0.0
half cycle
VIL.DIFF.MAX
VIL.DIFF.AC.MAX
tDVAC
time
Figure 2 : Definition of differential ac-swing and "time above ac level" tDVAC
8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)
[ Table 9 ] Defferential AC and DC Input Levels
Symbol
Parameter
DDR3-800/1066/1333/1600
min
max
unit
Note
VIHdiff
differential input high
+0.2
note 3
V
1
VILdiff
differential input low
note 3
-0.2
V
1
VIHdiff(AC)
differential input high ac
2 x (VIH(AC)-VREF)
note 3
V
2
VILdiff(AC)
differential input low ac
note 3
2 x (VREF - VIL(AC))
V
2
Notes:
1. Used to define a differential signal slew-rate.
2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a
reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective
limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Reter to "overshoot and Undersheet
Specification "
[ Table 10 ] Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS
Slew Rate [V/ns]
> 4.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
< 1.0
tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV
min
max
75
-
57
-
50
-
38
-
34
-
29
-
22
-
13
-
0
-
0
-
tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV
min
max
175
-
170
-
167
-
163
-
162
-
161
-
159
-
155
-
150
-
150
-
Page 15 of 59
Rev. 1.0 March 2009
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