K4B4G0446B Datasheet, PDF (45/59 Pages) Samsung semiconductor – DDP 4Gb B-die DDR3 SDRAM Specification

K4B4G0446B
K4B4G0846B
DDP 4Gb DDR3 SDRAM
[ Tabel 47 ] Timing Parameters by Speed Bin (Cont.)
Speed
Parameter
Symbol
DDR3-800
MIN
MAX
DDR3-1066
MIN
MAX
DDR3-1333
MIN
MAX
DDR3-1600
MIN
MAX
Command and Address Timing
DLL locking time
tDLLK
512
-
512
-
512
-
512
-
internal READ Command to PRECHARGE Command
delay
tRTP
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
Delay from start of internal write transaction to internal
read command
tWTR
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
WRITE recovery time
tWR
15
-
15
-
15
-
15
-
Mode Register Set command cycle time
tMRD
4
-
4
-
4
-
4
-
Mode Register Set command update delay
max
max
max
max
tMOD (12nCK,15ns
-
(12nCK,15ns
-
(12nCK,15ns
-
(12nCK,15ns
-
)
)
)
)
CAS# to CAS# command delay
tCCD
4
-
4
-
4
-
4
-
Auto precharge write recovery + precharge time
tDAL(min)
WR + roundup (tRP / tCK(AVG))
Multi-Purpose Register Recovery Time
tMPRR
1
-
1
-
1
-
1
-
ACTIVE to PRECHARGE command period
tRAS
See 13.3 " Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin" on page 37
ACTIVE to ACTIVE command period for 1KB page size
tRRD
max
(4nCK,10ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,6ns)
-
max
(4nCK,6ns)
-
ACTIVE to ACTIVE command period for 2KB page size
tRRD
max
(4nCK,10ns)
-
max
(4nCK,10ns)
-
max
(4nCK,7.5ns)
-
max
(4nCK,7.5ns)
-
Four activate window for 1KB page size
tFAW
40
-
37.5
-
30
-
30
-
Four activate window for 2KB page size
tFAW
50
-
50
-
45
-
40
-
Command and Address setup time to CK, CK refer-
enced to V_IH(AC) / V_IL(AC) levels
tIS(base)
200
-
125
-
Command and Address hold time from CK, CK refer-
enced to V_IH(AC) / V_IL(AC) levels
tIH(base)
275
-
200
-
Command and Address setup time to CK, CK refer-
enced to V_IH(AC) / V_IL(AC) levels
tIS(base)
AC150
200 + 150
-
125 + 150
-
Control & Address Input pulse width for each input
tIPW
900
-
780
-
65
140
65+125
620
-
TBD
-
-
TBD
-
-
TBD+125
-
-
560
-
Calibration Timing
Power-up and RESET calibration time
tZQinitI
512
-
512
-
512
-
512
-
Normal operation Full calibration time
tZQoper
256
-
256
-
256
-
256
-
Normal operation short calibration time
tZQCS
64
-
64
-
64
-
64
-
Reset Timing
Exit Reset from CKE HIGH to a valid command
tXPR
max(5nCK,
tRFC + 10ns)
-
max(5nCK,
tRFC + 10ns)
-
max(5nCK,
tRFC + 10ns)
-
max(5nCK,
tRFC + 10ns)
-
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked
DLL
tXS
max(5nCK,tR
FC + 10ns)
-
max(5nCK,tR
FC + 10ns)
-
max(5nCK,tR
FC + 10ns)
-
max(5nCK,tR
FC + 10ns)
-
Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
tDLLK(min)
-
Minimum CKE low width for Self refresh entry to exit
timing
tCKESR
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
tCKE(min) +
1tCK
-
Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE)
tCKSRE
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit
tCKSRX
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
max(5nCK,
10ns)
-
Units Note
nCK
e
e,18
ns
e
nCK
nCK
nCK
nCK
22
ns
e
e
e
ns
e
ns
e
ps
b,16
ps
b,16
ps b,16,27
ps
28
nCK
nCK
nCK
23
nCK
Page 45 of 59
Rev. 1.0 March 2009