K5A3X80YTC Datasheet, PDF (42/45 Pages) Samsung semiconductor – MCP MEMORY

K5A3x80YT(B)C
Preliminary
MCP MEMORY
SRAM TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1_S=OE=VIL, CS2_S=WE=VIH, UB or/and LB=VIL)
tRC
Address
Data Out
tAA
tOH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS1_S
tRC
tAA
tOH
tCO1
CS2_S
UB, LB
OE
Data out
High-Z
tCO2
tBA
tOE
tOLZ
tBLZ
tLZ
Data Valid
tHZ
tBHZ
tOHZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
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Revision 0.0
November 2002