K5A3X80YTC Datasheet, PDF (2/45 Pages) Samsung semiconductor – MCP MEMORY

K5A3x80YT(B)C
Preliminary
MCP MEMORY
Multi-Chip Package MEMORY
32M Bit (4Mx8/2Mx16) Dual Bank NOR Flash Memory / 8M(1Mx8/512Kx16) Full CMOS SRAM
FEATURES
• Power Supply voltage : 2.7V to 3.3V
• Organization
- Flash : 4,194,304 x 8 / 2,097,152 x 16 bit
- SRAM : 1,048,576 x 8 / 524,288 x 16 bit
• Access Time (@2.7V)
- Flash : 70 ns, SRAM : 55 ns
• Power Consumption (typical value)
- Flash Read Current : 14 mA (@5MHz)
Program/Erase Current : 15 mA
Standby mode/Autosleep mode : 5 µA
Read while Program or Read while Erase : 25 mA
- SRAM Operating Current : 22 mA
Standby Current : 0.5 µA
• Secode(Security Code) Block : Extra 64KB Block (Flash)
• Block Group Protection / Unprotection (Flash)
• Flash Bank Size : 8Mb / 24Mb , 16Mb / 16Mb
• Flash Endurance : 100,000 Program/Erase Cycles Minimum
• SRAM Data Retention : 1.5 V (min.)
• Industrial Temperature : -40°C ~ 85°C
• Package : 69-ball TBGA Type - 8 x 11mm, 0.8 mm pitch
1.2mm(max.) Thickness
GENERAL DESCRIPTION
The K5A3x80YT(B)C featuring single 3.0V power supply is a
Multi Chip Package Memory which combines 32Mbit Dual Bank
Flash and 8Mbit fCMOS SRAM.
The 32Mbit Flash memory is organized as 4M x8 or 2M x16 bit
and 8Mbit SRAM is organized as 1M x8 or 512K x16 bit. The
memory architecture of flash memory is designed to divide its
memory arrays into 71 blocks and this provides highly flexible
erase and program capability. This device is capable of reading
data from one bank while programming or erasing in the other
bank with dual bank organization.
The Flash memory performs a program operation in units of 8 bits
(Byte) or 16 bits (Word) and erases in units of a block. Single or
multiple blocks can be erased. The block erase operation is com-
pleted for typically 0.7sec.
The 8Mbit SRAM supports low data retention voltage for battery
backup operation with low data retention current.
The K5A3x80YT(B)C is suitable for the memory of mobile com-
munication system to reduce mount area. This device is available
in 69-ball TBGA Type package.
BALL CONFIGURATION
1 2 3 4 5 6 7 8 9 10
A ^N.C
N.C N.C
N.C
B N.C
A7
LB
WP/
ACC
WE
A8
A11
C
A3 A6 UB RESET CS2_S A19 A12 A15
D
A2 A5 A18 RY/BY A20 A9 A13 N.C
E
N.C A1 _{A4 A17}
A10 A14 N.C N.C
F
N.C A0 _{VSS DQ1}
DQ6 SA A16 N.C
G
CE_F
OE
DQ9
DQ3
DQ4
DQ13
DQ15
/A-1
BYTE_F
H
CS1_S DQ0 DQ10 Vcc_F Vcc_S DQ12 DQ7 Vss
J
DQ8 DQ2 DQ11 BYTES DQ5 DQ14
K ^N.C
N.C N.C
N.C
69 Ball TBGA , 0.8mm Pitch
Top View (Ball Down)
BALL DESCRIPTION
Ball Name
Description
A0 to A18 Address Input Balls (Common)
A-1, A19 to A20 Address Input Balls (Flash Memory)
DQ0 to DQ15 Data Input/Output Balls (Common)
RESET
Hardware Reset (Flash Memory)
WP/ACC
Write Protection / Acceleration Program
(Flash Memory)
Vcc_S
Vcc_F
Vss
UB
LB
BYTE_S
BYTE_F
SA
CE_F
CS1_S
CS2_S
WE
OE
RY/BY
N.C
Power Supply (SRAM)
Power Supply (Flash Memory)
Ground (Common)
Upper Byte Enable (SRAM)
Lower Byte Enable (SRAM)
BYTE_S Control (SRAM)
BYTE_F Control (Flash Memory)
Address Inputs (SRAM)
Chip Enable (Flash Memory)
Chip Enable (SRAM Low Active)
Chip Enable (SRAM High Active)
Write Enable (Common)
Output Enable (Common)
Ready/Busy (Flash memory)
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
-2-
Revision 0.0
November 2002