K5A3X80YTC Datasheet, PDF (3/45 Pages) Samsung semiconductor – MCP MEMORY

K5A3x80YT(B)C
ORDERING INFORMATION
Preliminary
MCP MEMORY
K5 A 3x80 Y T C - T 7 55
Samsung
MCP Memory
Device Type
Dual Bank Boot Block NOR
+ fCMOS SRAM
NOR Flash Density
(Bank Size), (Organization)
32 : 32Mbit, (8Mb, 24Mb)
(x8/x16 Selectable)
33 : 32Mbit, (16Mb, 16Mb)
(x8/x16 Selectable)
SRAM Density , Organization
8Mbit, x8/x16 Selectable
Operating Voltage Range
2.7V to 3.3V
SRAM Access Time
55 = 55 ns
Flash Access Time
7 = 70 ns
8 = 80 ns
Package
T = 69 TBGA
Version
C = 4th Generation
Block Architecture
T = Top Boot Block
B = Bottom Boot Block
Figure 1. FUNCTIONAL BLOCK DIAGRAM
Vcc_F
Vss
RESET
RD/BY
A0 to A18
(Common)
A-1,A19 to A20
BYTE_F
CE_F
OE
WE
Bank1
Address
I/O
Interface
&
Bank
Control
Bank2
Address
Clk gen.
X
Bank1
Dec
Cell Array
Y Dec
Bank1 Data-In/Out
Bank2 Data-In/Out
Y Dec
X
Bank2
Dec
Cell Array
Erase
Control
Program
Control
Latch &
Control
Latch &
Control
High
Voltage
Gen.
Precharge circuit.
SA
UB
LB
BYTE_S
CS1_S
CS2_S
Vcc_S
Vss
Row
select
Control
logic
Data
control
SRAM
Main Cell Array
(512K x16, 1M x8)
I/O Circuit
Column select
Bottom Boot Block
DQ0 to DQ7
DQ8 to DQ15
-3-
Revision 0.0
November 2002