K5A3X80YTC Datasheet, PDF (41/45 Pages) Samsung semiconductor – MCP MEMORY

K5A3x80YT(B)C
Preliminary
MCP MEMORY
SRAM AC CHARACTERISTICS
Parameter List
Read cycle time
Address access time
Chip select to output
Output enable to valid output
UB, LB Access Time
Read ^{Chip select to low-Z output}
UB, LB enable to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
UB, LB disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
UB, LB Valid to End of Write
Write _{Write pulse width}
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
Symbol
tRC
tAA
tCO1, tCO2
tOE
tBA
tLZ1, tLZ2
tBLZ
tOLZ
tHZ1, tHZ2
tBHZ
tOHZ
tOH
tWC
tCW
tAS
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
tOW
55ns
Min
Max
55
-
-
55
-
55
-
25
-
55
10
-
10
-
5
-
0
20
0
20
0
20
10
-
55
-
45
-
0
-
45
-
45
-
40
-
0
-
0
20
20
-
0
-
5
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc_S for data retention
Data retention current
Data retention set-up time
Recovery time
VDR
IDR
tSDR
tRDR
CS1_S≥Vcc_S-0.2V
Vcc_S=3.0V, CS1_S≥Vcc_S-0.2V
See data retention waveform
1.5
-
3.3
V
-
0.5
15
µA
0
-
tRC
-
-
ns
-
1. CS1_S≥Vcc_S-0.2V, CS2_S≥Vcc_S-0.2V(CS1_S controlled) or CS2_S≤0.2V(CS2_S controlled)
2. Typical values are measured at Vcc=3.0V, Ta=25°C , not 100% tested.
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Revision 0.0
November 2002