K5A3X80YTC Datasheet, PDF (12/45 Pages) Samsung semiconductor – MCP MEMORY

K5A3x80YT(B)C
Preliminary
MCP MEMORY
WE
A20∼A0(x16)/*
A20∼A-1(x8)
555H/
AAAH
2AAH/
555H
555H/
AAAH
00H/
00H
01H/
02H
DQ15∼DQ0
AAH
55H
90H
ECH
22oAr0H
22A2H
F0H
Manufacturer
Code
Device Code
(K5A3280Y)
Return to
Read Mode
NOTE: The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 6 for device code.
Figure 3. Autoselect Operation
Write (Program/Erase) Mode
Flash memory executes its program/erase operations by writing commands into the command register. In order to write the com-
mands to the register, CE_F and WE must be low and OE must be high. Addresses are latched on the falling edge of CE_F or WE
(whichever occurs last) and the data are latched on the rising edge of CE_F or WE (whichever occurs first). The device uses standard
microprocessor write timing.
Program
Flash memory can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the
Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first
two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the mem-
ory location and the data to be programmed at that location are written. The device automatically generates adequate program
pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is
not required to provide further controls or timings.
During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program
operation will cause data corruption at the corresponding location.
WE
A20∼A0(x16)/
A20∼A-1(x8)
DQ15-DQ0
RY/BY
555H/
AAAH
2AAH/
555H
555H/
AAAH
AAH
55H
Program
Address
A0H
Program
Data
Program
Start
Figure 4. Program Command Sequence
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Revision 0.0
November 2002