K5A3X80YTC Datasheet, PDF (11/45 Pages) Samsung semiconductor – MCP MEMORY

K5A3x80YT(B)C
Preliminary
MCP MEMORY
Flash DEVICE OPERATION
Byte/Word Mode
If the BYTE_F ball is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE_F ball is set at logical "0"
, the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 ball is used as an input for the LSB
(A-1) address ball.
Read Mode
Flash memory is controlled by Chip Enable (CE_F), Output Enable (OE) and Write Enable (WE). When CE_F and OE are low and WE
is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state
whenever CE_F or OE is high.
Standby Mode
Flash memory features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is dese-
lected by making CE_F high (CE_F = VIH). Refer to the DC characteristics for more details on stand-by modes.
Output Disable
The device outputs are disabled when OE is High (OE = VIH). The output balls are in high impedance state.
Automatic Sleep Mode
Flash memory features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 5µA of
current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When addresses
remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched
and always available to the system. When addresses are changed, the device provides new data without wait time.
Address
tAA + 50ns
Outputs
Data
Data
Data
Data
Data
Data
Auto Sleep Mode
Figure 2. Auto Sleep Mode Operation
Autoselect Mode
Flash memory offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode
allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm.
In addition, this mode allows the verification of the status of write protected blocks. The manufacturer and device code can be read
via the command register. The Command Sequence is shown in Table 5 and Figure 3. The autoselect operation of block protect ver-
ification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). If
Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address ball, it will produce a logical "1" at the device output DQ0
to indicate a write protected block or a logical "0" at the device output DQ0 to indicate a write unprotected block. To terminate the
autoselect operation, write Reset command (F0H) into the command register.
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Revision 0.0
November 2002