HD151TS201AT Datasheet, PDF (9/29 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set

HD151TS201AT
I²C Controlled Register Bit Map (cont.)
Byte2 PCI clock enable Register
Bit Description
7
(Reserved)
6
PCI6 Enable register
5
PCI5 Enable register
4
PCI4 Enable register
3
PCI3 Enable register
2
PCI2 Enable register
1
PCI1 Enable register
0
PCI0 Enable register
Contents
“1” = Enabled
“0” = Disabled
(Each PCI clock stops “Low”)
Default
0
1
1
1
1
1
1
1
Byte3 PCIF & USB, DOT enable Register
Bit Description
7
DOT output enable
6
USB output enable
5
Control of PCIF2 with PCISTOP#
4
Control of PCIF1 with PCISTOP#
3
Control of PCIF0 with PCISTOP#
2
PCIF2 output enable
1
PCIF1 output enable
0
PCIF0 output enable
Contents
Default
1 = Enable, 0 = Disable (DC Low fixed)
1
1 = Enable, 0 = Disable (DC Low fixed)
1
“1” = Not Free running.
0
When this bit is “1”, PCIF outputs are stopped by ₀
PCISTOP# pin.
“0” = Free running.
0
1 = Enable, 0 = Disable (DC Low fixed)
1
1 = Enable, 0 = Disable (DC Low fixed)
1
1 = Enable, 0 = Disable (DC Low fixed)
1
Byte4 66OUT, 3V66 Enable Register
Bit Description
7
Reserved
6
Reserved
5
3V66_0 Enable
4
3V66_1/VCH Enable
3
3V66_5 Enable
2
66OUT2/3V66_4 Enable
1
66OUT1/3V66_3 Enable
0
66OUT0/3V66_2 Enable
Contents
1 = Enable, 0 = Disable (DC Low fixed)
1 = Enable, 0 = Disable (DC Low fixed)
1 = Enable, 0 = Disable (DC Low fixed)
1 = Enable, 0 = Disable (DC Low fixed)
1 = Enable, 0 = Disable (DC Low fixed)
1 = Enable, 0 = Disable (DC Low fixed)
Default
0
0
1
1
1
1
1
1
Rev.1.00, Oct.21.2003, page 9 of 28