HD151TS201AT Datasheet, PDF (19/29 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set

HD151TS201AT
Pin Descriptions (cont.)
Pin name
REF
MULT0
PWRDWN#
USB48
DOT48
XIN
XOUT
SDATA
SCLK
IREF
3V66_0
3V66_1/VCH
66IN/3V66_5
66OUT[2:0]/
3V66[4:2]
No.
56
43
25
39
38
2
3
29
30
42
33
35
24
23,22,21
Type
OUTPUT
INPUT
INPUT
OUTPUT
OUTPUT
INPUT
OUTPUT
INPUT/
OUTPUT
INPUT
IN
OUTPUT
OUTPUT
IN/OUT
OUTPUT
Description
14.318MHz reference clock.
CPUCLK’s output current setting.
This pin is 150kΩ internal pull-up.
Power down pin. All circuits will be powered down.
(Output state of each output is shown in page Table.)
Asynchronous active low input pin used to power down the
device into low power state. The internal clocks are disabled
and VCO and the crystal are stopped.
3.3V 48 MHz USB clock output.
3.3V 48MHz DOT clock output.
XTAL input.
XTAL output. Don’t connect when an external clock is applied to
XIN.
Data input/output for I²C logic.
This pin is internal pull-up to VDD by 150KΩ resistor.
Clock input for I²C logic.
This pin is internal pull-up to VDD by 150KΩ resistor.
A precision resistor is attached to this pin which is connected to
internal current reference. A resistor is connected between this
pin and GNDIREF.
3.3 V 66 MHz clock.
3.3V clock output selectable with SM Bus byte0, bit5.
When Byte0 bit5 is at logic”1”, this pin is 48 MHz clock output.
When Byte0 bit5 is at logic”0”, this pin is 66 MHz clock output.
Default is 66 MHz output.
If S2 = 1, Input connection for 66OUT [2:0].
If S2 = 0, outputs fixed 66 MHz clock.
If S2 = 1, Buffered copies of 66IN.
If S2=0, outputs fixed 66MHz clock.
Rev.1.00, Oct.21.2003, page 19 of 28