HD151TS201AT Datasheet, PDF (11/29 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set

HD151TS201AT
I²C Controlled Register Bit Map (cont.)
Byte8 Clock Frequency Control Register
Bit Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
Clock Freq. Control bit2
2
Clock Freq. Control bit1
1
Clock Freq. Control bit0
0
Freq. Select Mode bit
Contents
See Table1
0 = Freq. is selected by latched input S2:0
1 = Freq. is selected by I²C Byte8 bit5:1
Default
X
X
0
0
0
0
0
0
Byte9 Control Register
Bit Description
Contents
Default
7
Reserved
0
6
Reserved
0
5
Reserved
0
4
Reserved
0
3
Spread Spectrum Control bit
0 = –0.5% (Default) 1 = –1.0%
0
2
3V66 & PCI Clock PLL select bit
“0” = CPU PLL
0
“1” = USB PLL
When this bit set to “1”, 3V66 & PCI clocks will
be supply from USB PLL. Not depended on
CPU PLL.
1
PLL N Divider Control bit9
PLL N Divider Control bit9
0
0
PLL N Divider Control bit8
PLL N Divider Control bit8
0
Note: Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.
Rev.1.00, Oct.21.2003, page 11 of 28