HD151TS201AT Datasheet, PDF (18/29 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set

HD151TS201AT
Pin Descriptions
Pin name
GND
VDD
VDDA
GNDA
CPUT[2:0]
CPUC[2:0]
CPUSTOP#
PCIF[2:0]
PCI[6:0]
PCISTOP#
S1, S0
S2
VTT_PWRGD#
No.
Type
4,9,15,20 Ground
31,36,41,47
1,8,14,19 Power
32,37,46,50
26
Power
27
Power
45,49,52 OUTPUT
44,48,51 OUTPUT
53
INPUT
7,6,5
OUTPUT
18,17,16,13 OUTPUT
12,11,10
34
INPUT
55,54
40
28
INPUT
INPUT
INPUT
Description
GND pins
Power supplies pins. Nominal 3.3 V.
Power supply for PLL core.
Power supply for PLL core.
“True” clocks of differential pair CPUCLK.
These pins are HCSL output.
“Complementary” clocks of differential pair CPUCLK.
These pins are HCSL output.
CPUCLK STOP pin. Active low input.
When asserted low, CPUT [2:0] clocks are synchronously
disabled in high state and CPUC [2:0] clocks are synchronously
disabled in a low state.
CPUSTOP# pin is 150 kΩ internal pulled-up.
Free running PCI clock 3.3 V output.
33 MHz clocks divided from 3V66.
3.3 V PCI clock outputs.
33 MHz clocks divided from 3V66.
PCICLK STOP pin. Active low input.
When asserted low, PCI [6:0] clocks are synchronously
disabled in low state. This pin does not effect PCIF [2:0] clocks
outputs if they are programmed to be PCIF clocks via the
device’s SM Bus interface.
PCISTOP# pin is 150 kΩ internal pulled-up.
Frequency selects input. See frequency table2 in page5.
Frequency selects input. See frequency table2 in page5.
This pin is 3 level input.
Qualifying input that latches S [2:0] and MULT0. When this
input is at a logic low, the S[2:0] and MULT0 are latched.
Rev.1.00, Oct.21.2003, page 18 of 28