HD151TS201AT Datasheet, PDF (8/29 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set

HD151TS201AT
I²C Controlled Register Bit Map
Byte0 Control Register
Bit Description
Contents
Default
7
Spread spectrum Enable
“1” = SSC ON
0
“0” = SSC OFF
6
CPUCLK Power down mode setting.
See Table4
0
See Table4.
5
VCH (pin35) Select 66 MHZ or 48 MHz “1” = 48 MHz
0
“0” = 66 MHz
4
CPUSTOP# status register
CPUSTOP# Reflects the current value of
1
external CPUSTOP# (pin53).
This bit is read only.
3
PCISTOP# Selection.
See Table5
Reflects the current value of the internal
1
PCISTOP# function when read. Internally
PCISTOP# is a logical AND function of the
internal SM Bus registers bit and the external
PCISTOP# (pin34).
2
Reflects the value of the S2 (pin40)
Frequency selects bit2, reflects the value of X
S2 (pin40). This bit is read only.
1
Reflects the value of the S1 (pin55)
Frequency selects bit1, reflects the value of X
S1 (pin55). This bit is read only.
0
Reflects the value of the S0(pin54)
Frequency selects bit0, reflects the value of X
S0 (pin54). This bit is read only.
Byte1 Control Register
Bit Description
Contents
Default
7
MULT0 (pin43) Value
MULT0 value. This bit is read only.
X
6
CPUCLK Power down mode setting. See Table4
0
See Table4.
5
Control of CPU2 with CPUSTOP#
“1” = Free running
0
4
Control of CPU1 with CPUSTOP#
“0” = Not free running.
0
When this bit is “0”, CPUT/C outputs are affected
3
Control of CPU0 with CPUSTOP#
by CPUSTOP# pin.
0
2
CPUT2/C2 Enable register
1
CPUT1/C1 Enable register
0
CPUT0/C0 Enable register
“1” = Enabled
1
“0” = Disabled
1
(CPUT stops “High” & CPUC stops “Low”)
1
Rev.1.00, Oct.21.2003, page 8 of 28