HD151TS201AT Datasheet, PDF (16/29 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set

HD151TS201AT
I²C Controlled Register Bit Map (cont.)
Byte20 PCI Skew Control Register 3
Bit Description
7
(Reserved)
6
PCI6 skew Early or Late
5
PCI5 skew Early or Late
4
PCI4 skew Early or Late
3
PCI3 skew Early or Late
2
PCI2 skew Early or Late
1
PCI1 skew Early or Late
0
PCI0 skew Early or Late
Contents
“0” = Early
“1” = Late
Byte21 Slew Rate Control Register
Bit Description
7
PCI clock slew rate controlbit1
6
PCI clock slew rate controlbit0
5
PCIF clock slew rate controlbit1
4
PCIF clock slew rate controlbit0
3
66OUT clock slew rate controlbit1
2
66OUT clock slew rate controlbit0
1
3V66 clock slew rate controlbit1
0
3V66 clock slew rate controlbit0
Contents
00 : Normal
01 : +
00 : Normal
01 : +
00 : Normal
01 : +
00 : Normal
01 : +
10 : ++
11 : –
10 : ++
11 : –
10 : ++
11 : –
10 : ++
11 : –
Byte22 Slew Rate Control Register
Bit Description
7
Reserved
6
Reserved
5
Reserved
4
Reserved
3
REF clock slew rate controlbit1
2
REF clock slew rate controlbit0
1
VCH clock slew rate controlbit1
0
VCH clock slew rate controlbit0
Contents
00 : Normal
01 : +
00 : Normal
01 : +
10 : ++
11 : –
10 : ++
11 : –
Rev.1.00, Oct.21.2003, page 16 of 28
Default
0
0
0
0
0
0
0
0
Default
0
0
0
0
0
0
0
0
Default
1
0
1
1
0
0
0
0