HD151TS201AT Datasheet, PDF (14/29 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set

HD151TS201AT
I²C Controlled Register Bit Map (cont.)
Byte14 Control Register
Bit Description
7
Reserved
6
DOT Clock Invert
5
USB clock Invert
4
VCH clock Invert
3
PCI clock Invert
2
66OUT clock Invert
1
3V66 clock Invert
0
CPU clock Invert
Contents
0=Normal, 1=Inverted
0=Normal, 1=Inverted
0=Normal, 1=Inverted
0=Normal, 1=Inverted
0=Normal, 1=Inverted
0=Normal, 1=Inverted
0=Normal, 1=Inverted
Default
0
0
0
0
0
0
0
0
Byte15 Control Register
Bit Description
7
REF clock enable
6
Control of PCI6 with PCISTOP#
5
Control of PCI5 with PCISTOP#
4
Control of PCI4 with PCISTOP#
3
Control of PCI3 with PCISTOP#
2
Control of PCI2 with PCISTOP#
1
Control of PCI1 with PCISTOP#
0
Control of PCI0 with PCISTOP#
Contents
Default
0 = Enable, 1 = Disable
0
“0” = Not Free running
0
When this bit is “0”, PCI outputs are stopped by ₀
PCISTOP# pin.
“1” = Free running.
0
0
0
0
0
Byte16 CPU Skew Control Register
Bit Description
7
(Reserved)
6
(Reserved)
5
CPU clock skew controlbit5
4
CPU clock skew controlbit4
3
CPU clock skew controlbit3
2
CPU clock skew controlbit2
1
CPU clock skew controlbit1
0
CPU clock skew controlbit0
Contents
00 : Delay 0ps
01 : Delay 250ps
10 : Ahead 500ps
11 : Ahead 250ps
0100 : Delay 0ps
0101 : Delay 500ps 0011 : Ahead 500ps
0110 : Delay 1000ps 0010 : Ahead 1000ps
0111 : Delay 1500ps 0001 : Ahead 1500ps
1000 : Delay 2000ps 0000 : Ahead 2000ps
Don’t set 1001 to 1111
Default
0
0
0
0
0
1
0
0
Rev.1.00, Oct.21.2003, page 14 of 28