HD151TS201AT Datasheet, PDF (15/29 Pages) Renesas Technology Corp – Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set

HD151TS201AT
I²C Controlled Register Bit Map (cont.)
Byte17 3V66 Skew Control Register
Bit Description
7
(Reserved)
6
(Reserved)
5
3V66 clock skew controlbit5
4
3V66 clock skew controlbit4
3
3V66 clock skew controlbit3
2
3V66 clock skew controlbit2
1
3V66 clock skew controlbit1
0
3V66 clock skew controlbit0
Contents
00 : Delay 0ps 11 : Ahead 500ps
01 : Delay 250ps 11 : Ahead 250ps
0100 : Delay 0ps
0101 : Delay 500ps 0011 : Ahead 500ps
0110 : Delay 1000ps 0010 : Ahead 1000ps
0111 : Delay 1500ps 0001 : Ahead 1500ps
1000 : Delay 2000ps 0000 : Ahead 2000ps
Don’t set 1001 to 1111
Default
0
0
0
0
0
0
1
0
Byte18 PCI Skew Control Register 1
Bit Description
7
(Reserved)
6
(Reserved)
5
PCI clock skew controlbit5
4
PCI clock skew controlbit4
3
PCI clock skew controlbit3
2
PCI clock skew controlbit2
1
PCI clock skew controlbit1
0
PCI clock skew controlbit0
Contents
00 : Delay 0ps 10 : Ahead 500ps
01 : Delay 250ps 11 : Ahead 250ps
0100 : Delay 0ps
0101 : Delay 500ps 0011 : Ahead 500ps
0110 : Delay 1000ps 0010 : Ahead 1000ps
0111 : Delay 1500ps 0001 : Ahead 1500ps
1000 : Delay 2000ps 0000 : Ahead 2000ps
Don’t set 1001 to 1111
Default
0
0
0
0
0
1
1
0
Byte19 PCI Skew Control Register 2
Bit Description
7
(Reserved)
6
PCI_F2 skew Early or Late
5
PCI_F1 skew Early or Late
4
PCI_F0 skew Early or Late
3
PCI clock skew controlbit3
2
PCI clock skew controlbit2
1
PCI clock skew controlbit1
0
PCI clock skew controlbit0
Contents
“0” = Early
“1” = Late
0100 : Delay 0ps
0101 : Delay 500ps 0011 : Ahead 500ps
0110 : Delay 1000ps 0010 : Ahead 1000ps
0111 : Delay 1500ps 0001 : Ahead 1500ps
1000 : Delay 2000ps 0000 : Ahead 2000ps
Don’t set 1001 to 1111
Default
0
0
0
0
0
1
0
0
Rev.1.00, Oct.21.2003, page 15 of 28