M37160M8 Datasheet, PDF (87/131 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP
8.13.1 OSCILLATION CONTROL
(1) Stop Mode
The built-in clock generating circuit is shown in Figure 8.13.2. When
the STP instruction is executed, the internal clock φ stops at HIGH.
At the same time, timers 3 and 4 are connected by hardware and
“FF16” is set in timer 3 and “0716” is set in timer 4. Select f(XIN)/16 or
f(XCIN)/16 as the timer 3 count source (set both bit 0 of timer mode
register 2 and bit 6 at address 00C716 to “0” before the execution of
the STP instruction). Moreover, set the timer 3 and timer 4 interrupt
enable bits to disabled (“0”) before execution of the STP instruction.
The oscillator restarts when an external interrupt is accepted. How-
ever, the internal clock φ keeps its HIGH level until timer 4 overflows,
allowing time for oscillation stabilization when a quartz-crystal oscil-
lator is used.
By settimg bit 7 of timer return setting register (address 00CC16) to
“1, ” an arbitrary value can be set to timer 3 and timer 4.
Bit 7 of clock control register 3 (address 021216) can switch Port P10
pin and CLKCONT. When CLKCONT pin is selected, “H” is output nor-
mally. When an external interrupt is recieved in the STP state, the
CLKcont pin goes back to “H” output.
(2) Wait Mode
When the WIT instruction is executed, the internal clock φ stops in
the HIGH level but the oscillator continues running. This wait state is
released at reset or when an interrupt is accepted (See note). Since
the oscillator does not stop, the next instruction can be executed
immediately.
Note: In the wait mode, the following interrupts are invalid.
• VSYNC interrupt
• OSD interrupt
• All timer interrupts using external clock input from port pin as count
source
• All timer interrupts using f(XIN)/2 or f(XCIN)/2 as count source
• All timer interrupts using f(XIN)/4096 or f(XCIN)/4096 as count source
• f(XIN)/4096 interrupt
• Multi-master I²C-BUS interface interrupt
• Data slicer interrupt
• A-D conversion interrupt
(3) Low-speed Mode
If the internal clock is generated from the sub-clock (XCIN), a low
power consumption operation can be realized by stopping only the
main clock XIN. To stop the main clock, set bit 6 (CM6) of the CPU
mode register (00FB16) to “1.” When the main clock XIN is restarted,
the program must allow enough time for oscillation to stabilize.
Note that in the low-power-consumption mode the XCIN-XCOUT
drivability can be reduced, allowing even lower power consumption.
To reduce the XCIN-XCOUT drivability, clear bit 5 (CM5) of the CPU
mode register (00FB16) to “0.” At reset, this bit is set to “1” and strong
drivability is selected to help the oscillation to start. When executing
an STP instruction, set this bit to “1” by software before initiating the
instruction.
Clock control register 3
b7 b6 b5 b4 b3 b2 b1 b0
0
0 0 0 0 0 Clock control register 3 (CC3) [Address 021216]
B
Name
Functions
0 to _{Fix these bits to "0"}
4
5 R,G,B,OUT Output amplitude
level selection bit (CC35)
0: 0V–VCC
1: 0V–About 0.6VCC
6 _{Fix this bit to "0"}
After reset R W
0 RW
0 RW
0 RW
7 _{P10 function-selection bit (Note)}
(CC37)
0: Clock control signal
1: P10 I/O
0 RW
Note: When used as the clock control signal, set the Port 1 Direction Register
(address 00C316) bit 0 to 1.
Fig.8.13.6 Ckock control register 3
Rev.1.01 2003.11.13 page 87 of 130