M37160M8 Datasheet, PDF (12/131 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP
8. FUNCTION BLOCK DESCRIPTION
8.1 CENTRAL PROCESSING UNIT (CPU)
This microcomputer uses the standard 740 Family instruction set.
Refer to the table of 740 Family addressing modes and machine
instructions or the SERIES 740 <Software> User’s Manual for de-
tails on the instruction set.
Availability of 740 Family instructions are as follows:
The FST, SLW instruction cannot be used.
The MUL, DIV, WIT and STP instructions can be used.
8.1.1 CPU Mode Register
The CPU mode register includes a stack page selection bit and inter-
nal system clock selection bit. The CPU mode register is allocated at
address 00FB16.
CPU Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 0 CPU mode register (CM) [Address 00FB16]
B
Name
0, 1 Processor mode bits
(CM0, CM1)
2 Stack page selection
bit (CM2) (See note1)
Functions
After reset R W
b1 b0
0 0: Single-chip mode
0 1:
0 RW
1 0: Not available
1 1:
0: 0 page
1: 1 page
1 RW
3, 4 Fix these bits to “1.”
1 RW
5 XCOUT drivability
selection bit (CM5)
0: LOW drive
1: HIGH drive
6 _{Main Clock (XIN) stop bit 0: Oscillating}
(CM6)
1: Stopped
1 RW
0 RW
7 Internal system clock 0: XIN selected
0 RW
selection bit
(high-speed mode)
(CM7) (See note2)
1: XCIN–XCOUT selected
or FSCIN input selected
(low-speed mode)
Note 1: This bit is set to “1” after the reset release.
2: XCIN-XCOUT and FSCIN are switched over using Clock
Control Register 2 (address 021116) bit 2.
Fig. 8.1.1 CPU Mode Register
Rev.1.01 2003.11.13 page 12 of 130