M37160M8 Datasheet, PDF (57/131 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP
The vertical display start position is determined by counting the hori-
zontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are
positive polarity (negative polarity), the count starts at the rising edge
(falling edge) of HSYNC signal after the fixed cycle of the rising edge
(falling edge) of VSYNC signal. So the interval from the rising edge
(falling edge) of VSYNC signal to the rising edge (falling edge) of HSYNC
signal needs enough time (2 machine cycles or more) to avoid jitter.
The polarity of HSYNC and VSYNC signals can select with the I/O po-
larity control register (address 00D816).
8 machine cycles
or more
VSYNC signal input
VSYNC control
signal in
microcomputer
Period of counting
HSYNC signal
HSYNC
signal input
8 machine cycles
or more
0.25 to 0.50 [µs]
( at f(XIN) = 8MHz)
(See note 2)
12345
Not count
When bits 0 and 1 of the I/O polarity control register
(address 00D816) are set to “1” (negative polarity)
Notes 1 : The vertical position is determined by counting falling edge of HSYNC
signal after rising edge of VSYNC control signal in the microcomputer.
2 : Do not generate falling edge of HSYNC signal near rising edge of
VSYNC control signal in microcomputer to avoid jitter.
3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or
more.
Fig. 8.10.7 Supplement Explanation for Display Position
Rev.1.01 2003.11.13 page 57 of 130