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M37160M8 Datasheet, PDF (62/131 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER | |||
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M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP
Both HSYNC cignal and VSYNC signal are negative-polarity input
HSYNC
Field
Field
determination
flag(Note)
Display dot line
selection bit
Display dot line
VSYNC and
(n â 1) field
VSYNC
(Odd-numbered)
control
signal
T1
in microcom-
puter
Upper :
VSYNC signal
(n) field
(Even-numbered)
T2
Lower :
VSYNC control
signal in
micro-
computer
(n + 1) field
(Odd-numbered)
T3
0.25 to 0.50[ µs] at
f(XIN) = 8 MHz
Odd
0
Even 0 (T2 > T1)
1
0
Odd
1 (T3 < T2)
1
When using the field determination flag, be sure to set bit 0 of the PWM mode register 1 (address 0208 16) to â0.â
Dot line 1
Dot line 0
Dot line 0
Dot line 1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
OSD1 mode
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
OSD2,CD OSD mode
When the display dot line selection bit is â0,â
the â â font is displayed at even field, the
â â font is displayed at odd field. Bit 6 of the
I/O polarity control register can be read as the
field determination flag : â1â is read at odd field,
â0â is read at even field.
OSD ROM font configuration diagram
Note : The field determination flag changes at a rising edge of the V SYNC control signal (negative-polarity input) in
the microcomputer.
Fig. 8.10.14 Relation between Field Determination Flag and Display Font
Rev.1.01 2003.11.13 page 62 of 130
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