M37160M8 Datasheet, PDF (38/131 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP
8.6.6 START Condition Generation Method
When the ESO bit of the I²C control register (address 00F916) is “1,”
execute a write instruction to the I²C status register (address 00F816)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “0002” and an SCL
is output for 1 byte. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 8.6.10 for the START condition
generation timing diagram, and Table 8.6.2 for the START condition/
STOP condition generation timing table.
I²C status register
write signal
SCL
SDA
BB flag
Setup
time
Hold time
Set time
for BB flag
Fig. 8.6.10 START Condition Generation Timing Diagram
8.6.7 STOP Condition Generation Method
When the ESO bit of the I²C control register (address 00F916) is “1,”
execute a write instruction to the I²C status register (address 00F816)
to set the MST bit and the TRX bit to “1” and the BB bit to “0”. A STOP
condition will then be generated. The STOP condition generation tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 8.6.11 for the
STOP condition generation timing diagram, and Table 8.6.2 for the
START condition/STOP condition generation timing table.
I²C status register
write signal
SCL
SDA
BB flag
Setup
time
Hold time
Reset time
for BB flag
Fig. 8.6.11 STOP Condition Generation Timing Diagram
Table 8.6.2 START Condition/STOP Condition Generation Tim-
ing Table
Item
Standard Clock Mode High-speed Clock Mode
Setup time
5.0 µs (20 cycles)
(START condition)
2.5 µs (10 cycles)
Setup time
(STOP condition)
Hold time
4.25 µs (17 cycles)
5.0 µs (20 cycles)
1.75 µs (7 cycles)
2.5 µs (10 cycles)
Set/reset time
for BB flag
3.0 µs (12 cycles)
1.5 µs (6 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses denotes the
number of φ cycles.
φ = 8.86/2 MHz at FSCIN = 4.43 MHz
Rev.1.01 2003.11.13 page 38 of 130