M37160M8 Datasheet, PDF (32/131 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP
8.6.2 I²C Address Register
The I²C address register (address 00F716) consists of a 7-bit slave
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition is detected.
(1) Bit 0: read/write bit (RBW)
Not used when comparing addresses in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I²C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
(2) Bits 1 to 7: slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
I²C Address Register
b7 b6 b5 b4 b3 b2 b1 b0
I²C address register (S0D) [Address 00F716]
B
Name
Functions
After reset R W
0 _{Read/write bit} <Only in 10-bit addressing (in slave) mode>
0
R—
(RBW)
The last significant bit of address data is
compared.
0: Wait the first byte of slave address after
START condition
(read state)
1: Wait the first byte of slave address after
RESTART condition (write state)
1 Slave address ^{<In both modes>}
to (SAD0 to SAD6) The address data is compared.
7
0
RW
Fig. 8.6.3 I²C Address Register
Rev.1.01 2003.11.13 page 32 of 130