M37160M8 Datasheet, PDF (37/131 Pages) Renesas Technology Corp – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

M37160M8/MA/MF-XXXSP/FP,M37160EFSP/FP
(8) Bit 7: Communication mode specification bit
(master/slave specification bit: MST)
This bit is used for master/slave specification in data communica-
tions. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are received,
and data communication is performed in synchronization with the
clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
The MST bit is cleared to “0” in any of the following conditions.
• Immediately after completion of 1-byte data transmission when
arbitration lost is detected
• When a STOP condition is detected.
• When occurence of a START condition is disabled by the START
condition duplication prevention function (Note).
• At reset
Note: The START condition duplication prevention function disables the START
condition generation, bit counter reset, and SCL output, when the follow-
ing condition is satisfied:
a START condition is set by another master device.
I²
b7
r
b3 b2 b1 b0
I²C status register (S1) [Address 00F816]
B
Name
Functions
After reset _{R W}
0 Last receive bit (LRB)
(See note)
1 General call detecting flag
(AD0) (See note)
2 Slave address comparison
flag (AAS) (See note)
3 Arbitration lost detecting flag
(AL) (See note)
4 I²C-BUS interface interrupt
request bit (PIN)
5 Bus busy flag (BB)
6, 7 Communication mode
specification bits
(TRX, MST)
0 : Last bit = “0 ”
1 : Last bit = “1 ”
Indeterminate _{R —}
(See note)
0 : No general call detected
0
R—
1 : General call detected _{(See note)}
0 : Address mismatch
0
R—
1 : Address match
(See note)
0 : Not detected
1 : Detected
0
R—
(See note)
0 : Interrupt request issued
1 : No interrupt request issued
1
RW
0 : Bus free
1 : Bus busy
0
RW
b7 b6
0 0 : Slave recieve mode
0 1 : Slave transmit mode
1 0 : Master recieve mode
1 1 : Master transmit mode
0
RW
Note : These bits and flags can be read out, but cannnot be written.
Fig. 8.6.8 I²C Status Register
SCL
PIN
IICIRQ
Fig. 8.6.9 Interrupt Request Signal Generation Timing
Rev.1.01 2003.11.13 page 37 of 130