M16C65C_15 Datasheet, PDF (82/112 Pages) Renesas Technology Corp – RENESAS MCU

M16C/65C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
(in wait state setting 2 φ + 3 φ, 2 φ + 4 φ, 3φ + 4 φ, and 4 φ + 5 φ, and
when accessing external area)
Read timing
t cyc
V_CC1 = V_CC2 = 5V
BCLK
CSi
ADi
BHE
ALE
td(BCLK-CS)
25ns(max.)
td(BCLK-AD)
25ns(max.)
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
-4ns(min.)
RD
DBi
Hi-Z
Write timing
tcyc
td(BCLK-RD)
25ns(max.)
tac4(RD-DB)
(n × tcyc-45)ns(max.)
tsu(DB-RD)
50ns(min.)
th(BCLK-CS)
0ns(min.)
th(BCLK-AD)
0ns(min.)
th(RD-AD)
0ns(min.)
th(BCLK-RD)
0ns(min.)
th(RD-DB)
0ns(min.)
BCLK
td(BCLK-CS)
25ns(max.)
CSi
ADi
BHE
ALE
td(BCLK-AD)
25ns(max.)
td(BCLK-ALE)
15ns(max.)
th(BCLK-ALE)
-4ns(min.)
WR, WRL
WRH
DBi
Hi-Z
td(BCLK-WR)
25ns(max.)
td(BCLK-DB)
40ns(max.)
th(BCLK-CS)
0ns(min.)
th(BCLK-AD)
0ns(min.)
th(WR-AD)
(0.5 × tcyc -10)ns(min.)
th(BCLK-WR)
0ns(min.)
1
tcyc =
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 5V
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V
y Output timing voltage: VOL = 0.4 V, VOH = 2.4 V
Figure 5.18 Timing Diagram
td(DB-WR)
{(n-0.5) × tcyc -40}ns(min.)
th(WR-DB)
(0.5 × tcyc -20)ns(min.)
n: 3 (when 2 φ + 3 φ)
4 (when 2 φ + 4 φ or 3 φ + 4 φ)
5 (when 4 φ + 5 φ)
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 82 of 109