M16C65C_15 Datasheet, PDF (103/112 Pages) Renesas Technology Corp – RENESAS MCU

M16C/65C Group
5. Electrical Characteristics
Memory Expansion Mode and Microprocessor Mode
V_CC1 = V_CC2 = 3V
(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
td(BCLK-CS)
50ns(max.)
tcyc
th(RD-CS)
(0.5 × tcyc-10)ns(min.)
th(BCLK-CS)
0ns(min.)
td(AD-ALE)
(0.5 × tcyc-40ns(min.)
th(ALE-AD)
(0.5 × tcyc-15ns(min.)
Address
td(BCLK-AD)
50ns(max.)
td(AD-RD)
0ns(min.)
Data input
tdz(RD-AD)
8ns(max.) _tac3(RD-DB)
tsu(DB-RD)
{(n-0.5) × tcyc-60}ns(max.) 60ns(min.)
th(RD-DB)
0ns(min.)
Address
th(BCLK-AD)
0ns(min.)
td(BCLK-ALE)
25ns(max.)
th(BCLK-ALE)
-4ns(min.)
td(BCLK-RD)
40ns(max.)
th(RD-AD)
(0.5 × tcyc-10)ns(min.)
th(BCLK-RD)
0ns(min.)
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR, WRL,
WRH
WR, WRL,
td(BCLK-CS)
50ns(max.)
Address
td(AD-ALE)
(0.5 × tcyc-40ns(min.)
td(BCLK-AD)
50ns(max.)
tcyc
th(WR-CS)
th(BCLK-CS)
0ns(min.)
(0.5 × tcyc-10)ns(min.)
td(BCLK-DB)
50ns(max.)
Data output
td(DB-WR)
{(n-0.5) × tcyc-50}ns(min.)
Address
th(WR-DB)
(0.5 × tcyc-25)ns(min.)
th(BCLK-AD)
0ns(min.)
td(BCLK-ALE) th(BCLK-ALE)
25ns(max.)
-4ns(min.)
td(AD-WR)
0ns(min.)
td(BCLK-WR)
40ns(max.)
th(WR-AD)
(0.5 × tcyc-15)ns(min.)
th(BCLK-WR)
0ns(min.)
tcyc =
1
f(BCLK)
Measuring conditions
y VCC1 = VCC2 = 3V
y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V
y Output timing voltage: VOL = 1.5 V, VOH = 1.5 V
Figure 5.32 Timing Diagram
n: 2 (when 2 waits)
3 (when 3 waits)
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 103 of 109