M16C65C_15 Datasheet, PDF (81/112 Pages) Renesas Technology Corp – RENESAS MCU

M16C/65C Group
5. Electrical Characteristics
V_CC1 = V_CC2 = 5 V
Switching Characteristics
(V_CC1 = V_CC2 = 5 V, V_SS = 0 V, at T_opr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.4.4 In Wait State Setting 2φ + 3φ, 2φ + 4φ, 3φ + 4φ, and 4φ + 5φ, and When
Accessing External Area
Table 5.39 Memory Expansion Mode and Microprocessor Mode (in Wait State Setting 2 φ + 3 φ, 2 φ
+ 4φ, 3φ + 4φ, and 4φ + 5φ, and When Accessing External Area)
Symbol
Parameter
Measuring
Condition
Standard
Min.
Max.
Unit
t_d(BCLK-AD) Address output delay time
25
ns
t_h(BCLK-AD) Address output hold time (in relation to BCLK)
0
ns
t_h(RD-AD)
Address output hold time (in relation to RD)
0
ns
t_h(WR-AD)
Address output hold time (in relation to WR)
(Note 2)
ns
t_d(BCLK-CS) Chip select output delay time
25
ns
t_h(BCLK-CS) Chip select output hold time (in relation to BCLK)
0
ns
t_d(BCLK-ALE) ALE signal output delay time
15
ns
t_h(BCLK-ALE)
t_d(BCLK-RD)
ALE signal output hold time
RD signal output delay time
See
-4
ns
Figure 5.14
25
ns
t_h(BCLK-RD) RD signal output hold time
0
ns
t_d(BCLK-WR) WR signal output delay time
25
ns
t_h(BCLK-WR) WR signal output hold time
0
ns
t_d(BCLK-DB) Data output delay time (in relation to BCLK)
40
ns
t_d(DB-WR)
Data output delay time (in relation to WR)
(Note 1)
ns
t_h(WR-DB)
Data output hold time (in relation to WR) ⁽³⁾
(Note 4)
ns
Notes:
1. Calculated according to the BCLK frequency as follows:
-⁽--ⁿ----–-----0---.-5----⁾---^×-----1---0---⁹- – 40[ns]
f_(BCLK)
n is 3 for 2φ + 3φ, 4 for 2φ + 4φ, 4 for 3φ + 4φ, and 5 for 4φ + 5φ.
2. Calculated according to the BCLK frequency as follows:
0----.-5----×_{-----1---0----}⁹ _{– 10[ns]}
f_(BCLK)
3. This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = −CR × ln(1 − V_OL/V_CC2)
by a circuit of the right figure.
For example, when V_OL = 0.2V_CC2, C = 30 pF, R = 1 kΩ, hold
time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2V_CC2/V_CC2)
= 6.7 ns.
R
DBi
C
4. Calculated according to the BCLK frequency as follows: ^{0----.-5----×}-----1---0----⁹ – 20[ns]
f_(BCLK)
Hold time is equal to or less than 0 ns when the BCLK frequency exceeds 25 MHz.
R01DS0015EJ0110 Rev.1.10
Jul 31, 2012
Page 81 of 109