4518 Datasheet, PDF (79/160 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4518 Group
MR3
MR2
MR1
MR0
Clock control register MR
at reset : 11112
at RAM back-up : 11112
MR3 MR2
Operation mode
0 0 Through mode (frequency not divided)
Operation mode selection bits
0 1 Frequency divided by 2 mode
1 0 Frequency divided by 4 mode
1 1 Frequency divided by 8 mode
0
Main clock (f(XIN)) oscillation enabled
Main clock f(XIN) oscillation circuit control bit
1
Main clock (f(XIN)) oscillation stop
0
Main clock (f(XIN))
System clock oscillation source selection bit
1
Main clock (f(RING))
R/W
TAMR/
TMRA
Clock control register RG
RG0 On-chip oscillator (f(RING)) control bit
at reset : 02
at RAM back-up : 02
0
On-chip oscillator (f(RING)) oscillation enabled
1
On-chip oscillator (f(RING)) oscillation stop
W
TRGA
Timer control register PA
PA0 Prescaler control bit
at reset : 02
0
Stop (state initialized)
1
Operating
at RAM back-up : 02
W
TPAA
W13
W12
W11
W10
Timer control register W1
Timer 1 count auto-stop circuit selection
bit
(Note 2)
Timer 1 control bit
Timer 1 count source selection bits
at reset : 00002
at RAM back-up : state retained
0 Timer 1 count auto-stop circuit not selected
1 Timer 1 count auto-stop circuit selected
0 Stop (state retained)
1 Operating
W11 W10
Count source
0 0 Instruction clock (INSTCK)
0 1 Prescaler output (ORCLK)
1 0 XIN input
1 1 CNTR0 input
R/W
TAW1/TW1A
W23
W22
Timer control register W2
CNTR0 output signal selection bit
Timer 2 control bit
W21
W20
Timer 2 count source selection bits
at reset : 00002
at RAM back-up : state retained
0 Timer 1 underflow signal divided by 2 output
1 Timer 2 underflow signal divided by 2 output
0 Stop (state retained)
1 Operating
W21 W20
Count source
0 0 System clock (STCK)
0 1 Prescaler output (ORCLK)
1 0 Timer 1 underflow signal (T1UDF)
1 1 PWM signal (PWMOUT)
R/W
TAW2/TW2A
Note 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10=“1”).
Rev.3.01 2005.06.15 page 79 of 157
REJ03B0008-0301