4518 Datasheet, PDF (154/160 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4518 Group
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Unit
Min.
Typ.
Max.
VRST– Detection voltage
Ta = 25 °C
3.3
3.5
3.7
V
(reset occurs) (Note 1)
Mask ROM version
2.7
4.2
One Time PROM version
2.6
4.2
VRST+ Detection voltage
Ta = 25 °C
3.5
3.7
3.9
V
(reset release) (Note 2)
Mask ROM version
2.9
4.4
One Time PROM version
2.8
4.4
VRST+– Detection voltage hysteresis
0.2
V
VRST–
IRST
Operation current (Note 3) VDD = 5 V
50
100
µA
VDD = 3 V
30
60
TRST
Detection time
VDD → (VRST– – 0.1 V) (Note 4)
0.2
1.2
ms
Notes 1: The detected voltage (VRST–) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling.
2: The detected voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs.
3: When the voltage drop detection circuit is used (VDCE pin = “H”), IRST is added to IDD (power current).
4: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST– – 0.1 V].
BASIC TIMING DIAGRAM
Machine cycle
Mi
Parameter
Pin (signal) name
Mi+1
System clock
STCK
Port D output
Port D input
D0–D7
D0–D7
Ports P0, P1, P2, P3,
P6 output
P00–P03
P10–P13
P20–P23
P30, P31
P60–P63
Ports P0, P1, P2, P3,
P6 input
P00–P03
P10–P13
P20–P23
P30, P31
P60–P63
Interrupt input
INT0, INT1
Rev.3.01 2005.06.15 page 154 of 157
REJ03B0008-0301