4518 Datasheet, PDF (58/160 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4518 Group
(1) Power-on reset
Reset can be automatically performed at power on (power-on re-
set) by the built-in power-on reset circuit. When the built-in
power-on reset circuit is used, the time for the supply voltage to
rise from 0 V until the value of supply voltage reaches the minimum
operating voltage must be set to 100 µs or less.
If the rising time exceeds 100 µs, connect a capacitor between the
RESET pin and VSS at the shortest distance, and input “L” level to
RESET pin until the value of supply voltage reaches the minimum
operating voltage.
100 µs or less
VDD (Note 3)
(Note 1)
(Note 2)
RESET pin
(Note 1)
Pull-up transistor
Internal reset signal
Power-on reset circuit
Voltage drop detection circuit
Watchdog reset signal
Power-on reset circuit output
Internal reset signal
WEF
SRST instruction
Reset
state
Power-on Reset released
Notes 1:
This symbol represents a parasitic diode.
2: Applied potential to RESET pin must be VDD or less.
3: Keep the value of supply voltage to the minimum value
or more of the recommended operating conditions.
Fig. 48 Structure of reset pin and its peripherals,, and power-on reset operation
Table 1 Port state at reset
Name
D0–D5
D6/CNTR0
D7/CNTR1
P00–P03
P10–P13
P20/SCK, P21/SOUT, P22/SIN
P30/INT0, P31/INT1
P60/AIN0–P63/AIN3
Function
D0–D5
D6
D7
P00–P03
P10–P13
P20–P22
P30, P31
P60–P63
Notes 1: Output latch is set to “1.”
2: Output structure is N-channel open-drain.
3: Pull-up transistor is turned OFF.
State
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2)
High-impedance (Notes 1, 2, 3)
High-impedance (Notes 1, 2, 3)
High-impedance (Note 1)
High-impedance (Note 1)
High-impedance (Note 1)
Rev.3.01 2005.06.15 page 58 of 157
REJ03B0008-0301