4518 Datasheet, PDF (50/160 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4518 Group
(7) A/D conversion timing chart
Figure 38 shows the A/D conversion timing chart.
ADST instruction
A/D conversion
completion flag (ADF)
DAC operation signal
Fig. 38 A/D conversion timing chart
2 machine cycles + 10/f(ADCK)
(8) How to use A/D conversion
How to use A/D conversion is explained using as example in which
the analog input from P60/AIN0 pin is A/D converted, and the high-
order 4 bits of the converted data are stored in address M(Z, X, Y)
= (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1),
and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM.
The A/D interrupt is not used in this example.
Instruction clock/6 is selected as the A/D converter operation clock.
➀ Select the AIN0 pin function with the bit 0 of the register Q2. Se-
lect the AIN0 pin function and A/D conversion mode with the
register Q1. Also, the instruction clock divided by 6 is selected
with the register Q3. (refer to Figure 39)
➁ Execute the ADST instruction and start A/D conversion.
➂ Examine the state of ADF flag with the SNZAD instruction to de-
termine the end of A/D conversion.
➃ Transfer the low-order 2 bits of converted data to the high-order
2 bits of register A (TALA instruction).
➄ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2).
➅ Transfer the high-order 8 bits of converted data to registers A
and B (TABAD instruction).
➆ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1).
➇ Transfer the contents of register B to register A, and then, store
into M(Z, X, Y) = (0, 0, 0).
(Bit 3)
(Bit 0)
✕ ✕ ✕ 1 A/D control register Q2
AIN0 pin function selected
(Bit 3)
00
(Bit 0)
0 0 A/D control register Q1
AIN0 pin selected
A/D conversion mode
(Bit 3)
✕0
(Bit 0)
0 0 ^{A/D control register Q3}
Frequency divided by 6
Instruction clock
✕: Set an arbitrary value.
Fig. 39 Setting registers
Rev.3.01 2005.06.15 page 50 of 157
REJ03B0008-0301