4518 Datasheet, PDF (16/160 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4518 Group
FUNCTION BLOCK OPERATIONS
CPU
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4-
bit data addition, comparison, AND operation, OR operation, and
bit manipulation.
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, ex-
change, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a carry
with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction. The
value of A0 is stored in carry flag CY with the RAR instruction (Fig-
ure 2).
Carry flag CY can be set to “1” with the SC instruction and cleared
to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit
data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data transfer
with register B used as the high-order 4 bits and register A as the
low-order 4 bits (Figure 3).
Register E is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register A and
is used as a pointer within the specified page when the TABP p,
BLA p, or BMLA p instruction is executed. Also, when the TABP p
instruction is executed, the high-order 2 bits of the reference data
in ROM is stored to the low-order 2 bits of register D, and the con-
tents of the high-order 1 bit of register D is “0”. (Figure 4).
Register D is undefined after system is released from reset and re-
turned from the RAM back-up. Accordingly, set the initial value.
(CY)
(M(DP))
Addition
<Carry>
ALU
(A)
<Result>
Fig. 1 AMC instruction execution example
<Set>
<Clear>
SC instruction RC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B TAB instruction Register A
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
B3 B2 B1 B0
A3 A2 A1 A0
Register B TBA instruction Register A
Fig. 3 Registers A, B and register E
TABP p instruction
ROM
Specifying address
8
4
0
PCH
p6 p5 p4 p3 p2 p1 p0
PCL
DR2 DR1DR0 A3 A2 A1 A0
Immediate field
value p
The contents of The contents of
register D
register A
Fig. 4 TABP p instruction execution example
Low-order 4bits
Register A (4)
Middle-order 4 bits
Register B (4)
High-order 2 bits
Register D (3)
High-order 1 bit of
register D is “0”.
Rev.3.01 2005.06.15 page 16 of 157
REJ03B0008-0301