4518 Datasheet, PDF (25/160 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4518 Group
EXTERNAL INTERRUPTS
The 4518 Group has the external 0 interrupt and external 1 inter-
rupt.
An external interrupt request occurs when a valid waveform is input
to an interrupt input pin (edge detection).
The external interrupt can be controlled with the interrupt control
registers I1 and I2.
Table 7 External interrupt activated conditions
Name
Input pin
Activated condition
External 0 interrupt P30/INT0
External 1 interrupt P31/INT1
When the next waveform is input to P30/INT0 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
When the next waveform is input to P31/INT1 pin
• Falling waveform (“H”→“L”)
• Rising waveform (“L”→“H”)
• Both rising and falling waveforms
Valid waveform
selection bit
I11
I12
I21
I22
(Note 1)
P30/INT0
I13
(Note 1)
P31/INT1
I23
I12
Falling
0
1
Rising
K20
I22
Falling
0
1
Rising
K22
One-sided edge
I11
detection circuit
0
1
Both edges
detection circuit
(Note 2)
Level detection circuit
(Note 3)
Edge detection circuit
EXF0
External 0
interrupt
Period measurement
circuit input
Timer 1 count start
K21 ^{synchronous circuit}
0
Key-on wakeup
1
Skip decision
(SNZI0 instruction)
One-sided edge
detection circuit
I21
0
1
Both edges
detection circuit
(Note 2)
Level detection circuit
(Note 3)
Edge detection circuit
EXF1
External 1
interrupt
Timer 3 count start
synchronous circuit
K23
0
Key-on wakeup
1
Skip decision
(SNZI1 instruction)
Notes 1:
This symbol represents a parasitic diode on the port.
2: I12 (I22) = 0: “L” level detected
I12 (I22) = 1: “H” level detected
3: I12 (I22) = 0: Falling edge detected
I12 (I22) = 1: Rising edge detected
Fig. 17 External interrupt circuit structure
Rev.3.01 2005.06.15 page 25 of 157
REJ03B0008-0301