4518 Datasheet, PDF (44/160 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER

4518 Group
q^{Waveform extension function of CNTR1 output “H” interval: Invalid (W42 = “0”),}
CNTR1 output: valid (W43 = “1”),
Count source: XIN input selected (W40 = “0”),
Reload register R4L: “0316”
Reload register R4H: “0216”
Timer 4 count start timing
Machine cycle _Mi
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Register W41
Timer 4 count value
(Reload register)
Timer 4
underflow signal
PWM signal
Mi+1
Mi+2
TW4A instruction execution cycle (W41) ← 1
0316
(R4L)
0216 0116 0016 0216 0116 0016 0316 0216 0116
(R4H)
(R4L)
Timer 4 count start timing
Timer 4 count stop timing
Machine cycle
Mi
System clock
f(STCK)=f(XIN)/4
XIN input
(count source selected)
Mi+1
TW4A instruction execution cycle (W41) ← 0
Register W41
Timer 4 count value
(Reload register)
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016
(R4H)
(R4L)
0216
(R4H)
Timer 4
underflow signal
PWM signal
(Note 1)
Mi+2
Timer 4 count stop timing
Notes 1: In order to stop timer 4 at CNTR1 output valid (W43 = “1”), avoid a timing when timer 4 underflows.
If these timings overlap, a hazard may occur in a CNTR1 output waveform.
2: At CNTR1 output valid, timer 4 stops after “H” interval of PWM signal set by reload register R4H is output.
Fig. 33 Timer 4 count start/stop timing
Rev.3.01 2005.06.15 page 44 of 157
REJ03B0008-0301