|
4518 Datasheet, PDF (74/160 Pages) Renesas Technology Corp – SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER | |||
|
◁ |
4518 Group
16 P30/INT0 pin
ⶠNote [1] on bit 3 of register I1
When the input of the INT0 pin is controlled with the bit 3 of reg-
ister I1 in software, be careful about the following notes.
⸠Note on bit 2 of register I1
When the interrupt valid waveform of the P30/INT0 pin is
changed with the bit 2 of register I1 in software, be careful about
the following notes.
⢠Depending on the input state of the P30/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the bit 3 of regis-
ter I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to â0â (refer to
Figure 66 â) and then, change the bit 3 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
â0â after executing at least one instruction (refer to Figure 66 â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 66 â).
⢠Depending on the input state of the P30/INT0 pin, the external 0
interrupt request flag (EXF0) may be set when the bit 2 of regis-
ter I1 is changed. In order to avoid the occurrence of an
unexpected interrupt, clear the bit 0 of register V1 to â0â (refer to
Figure 68â) and then, change the bit 2 of register I1.
In addition, execute the SNZ0 instruction to clear the EXF0 flag to
â0â after executing at least one instruction (refer to Figure 68â).
Also, set the NOP instruction for the case when a skip is per-
formed with the SNZ0 instruction (refer to Figure 68â).
LA 4
TV1A
LA 8
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (1âââ2)
; Control of INT0 pin input is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
â : these bits are not used here.
Fig. 66 External 0 interrupt program example-1
â· Note [2] on bit 3 of register I1
When the bit 3 of register I1 is cleared to â0â, the RAM back-up
mode is selected and the input of INT0 pin is disabled, be careful
about the following notes.
LA 4
TV1A
LA 12
TI1A
NOP
SNZ0
NOP
; (âââ02)
; The SNZ0 instruction is valid ........... â
; (â1ââ2)
; Interrupt valid waveform is changed
........................................................... â
; The SNZ0 instruction is executed
(EXF0 flag cleared)
........................................................... â
â : these bits are not used here.
Fig. 68 External 0 interrupt program example-3
⢠When the input of INT0 pin is disabled (register I13 = â0â), set the
key-on wakeup function to be invalid (register K20 = â0â) before
system enters to the RAM back-up mode. (refer to Figure 67â).
LA 0
TK2A
DI
EPOF
POF
; (âââ02)
; Input of INT0 key-on wakeup invalid .. â
; RAM back-up
â : these bits are not used here.
Fig. 67 External 0 interrupt program example-2
Rev.3.01 2005.06.15 page 74 of 157
REJ03B0008-0301
|
▷ |