H8S-2258 Datasheet, PDF (759/1071 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 16 I²C Bus Interface (IIC) (Option)
16.4.8 Operation Using the DTC
The I²C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/W bit, confirmation of reception with acknowledge bit, indication of
the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in
conjunction CPU processing by means of interrupts.
Table 16.5 shows some example of processing using the DTC. These examples assume that the
number of transfer data bytes is know in slave mode.
Table 16.5 Flags and Transfer States
Item
Master Transmit Master Receive Slave Transmit
Mode
Mode
Mode
Slave Receive
Mode
Slave address + Transmission by Transmission by Reception by CPU Reception by CPU
R/W bit
DTC (ICDR write) CPU (ICDR write) (ICDR read)
(ICDR read)
Transmission/
reception
Dummy data 
Processing by 

read
CPU (ICDR read)
Actual data
Transmission by Reception by
Transmission by
transmission/rec DTC (ICDR write) DTC (ICDR read) DTC (ICDR write)
eption
Reception by DTC
(ICDR read)
Dummy data 

Processing by DTC 
(H'FF) write
(ICDR write)
Last frame
processing
Not necessary
Reception by
Not necessary
CPU (ICDR read)
Reception by CPU
(ICDR read)
Transfer request 1st time: Clearing Not necessary
processing after by CPU
last frame
2nd time: End
processing
condition issuance
by CPU
Automatic clearing Not necessary
on detection of end
condition during
transmission of
dummy data (H'FF)
Setting of
number of DTC
transfer data
frames
Transmission: Reception: Actual Transmission:
Reception: Actual
Actual data count data count
Actual data count + data count
+ 1 (+ 1 equivalent
1 (+ 1 equivalent to
to slave address +
dummy data (H'FF))
R/W bits)
Rev. 5.00 Aug 08, 2006 page 673 of 982
REJ09B0054-0500