H8S-2258 Datasheet, PDF (758/1071 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 16 I²C Bus Interface (IIC) (Option)
16.4.7 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 16.19 shows the IRIC set timing and SCL control.
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I²C bus format, no wait)
SCL
7
8
9
1
2
SDA
7
8
A
IRIC
1
2
User processing
Write to ICDR (transmit) Clear IRIC
or read ICDR (receive)
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I²C bus format, wait inserted)
SCL
8
9
1
2
SDA
8
IRIC
A
1
2
User processing
Clear Write to ICDR (transmit) _Clear
IRIC or read ICDR (receive) _IRIC
(c) When FS = 1 and FSX = 1 (synchronous serial format)
SCL
7
8
1
2
SDA
7
8
IRIC
1
2
User processing
Write to ICDR (transmit) _{Clear IRIC}
or read ICDR (receive)
Figure 16.19 IRIC Setting Timing and SCL Control
Rev. 5.00 Aug 08, 2006 page 672 of 982
REJ09B0054-0500