H8S-2258 Datasheet, PDF (744/1071 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 16 I²C Bus Interface (IIC) (Option)
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
IRIC
IRTR
ICDRT
ICDRS
Generate start
condition
[5]
Interrupt
request
1
2
3
4
5
6
7
8
9
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Slave address
R/W [7]
A
Interrupt
request
1
2
Bit 7 Bit 6
Data 1
Address + R/W
Address + R/W
Data 1
Data 1
Note: Do not write data
to ICDR.
User processing
[4] Write BBSY = 1
and SCP = 0
(generate start
condition)
[6] ICDR write
[6] IRIC clearance
[9] ICDR write
[9] IRIC clearance
Figure 16.8 Example of Master Transmit Mode Operation Timing (MLS = WAIT = 0)
SCL
(Master output)
89
SDA
(Master output)
Bit 0
Data 1 ^[7]
SDA
(Slave output)
A
1 234 5 67 89
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Data 2
[10]
A
Generate start
condition
IRIC
IRTR
ICDR
Data 1
Data 2
User processing
[9] ICDR write
[9] IRIC clearance
[11] ACKB read
[12] Write BBSY = 0
and SCP = 0
(generate stop
[12] IRIC clearance condition)
Figure 16.9 Example of Master Transmit Mode Stop Condition Generation Timing
(MLS = WAIT = 0)
Rev. 5.00 Aug 08, 2006 page 658 of 982
REJ09B0054-0500