H8S-2258 Datasheet, PDF (265/1071 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 7 Bus Controller
7.5.1 On-Chip Memory (ROM, RAM) Access Timing
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Figure 7.4 shows the on-chip memory access cycle. Figure 7.5 shows the
pin states.
φ
Internal address bus
Bus cycle
T₁
Address
Read
access
Internal read signal
Internal data bus
Read data
Write
access
Internal write signal
Internal data bus
Write data
Figure 7.4 On-5Chip Memory Access Cycle
Bus cycle
T₁
φ
Address bus
Unchanged
AS
High
RD
High
HWR, LWR
High
Data bus
High-impedance state
Figure 7.5 Pin States during On-Chip Memory Access
Rev. 5.00 Aug 08, 2006 page 179 of 982
REJ09B0054-0500