H8S-2258 Datasheet, PDF (72/1071 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Figure 13.3 Interval Timer Mode Operation ............................................................................. 475
Figure 13.4 Timing of OVF Setting........................................................................................... 475
Figure 13.5 Timing of WOVF Setting....................................................................................... 476
Figure 13.6 Writing to TCNT, TCSR ........................................................................................ 477
Figure 13.7 Writing to RSTCSR ............................................................................................... 478
Figure 13.8 Contention between TCNT Write and Increment................................................... 478
Section 14 IEBus Controller (IEB) [H8S/2258 Group]
Figure 14.1 Block Diagram of IEB............................................................................................ 482
Figure 14.2 Transfer Signal Format........................................................................................... 486
Figure 14.3 Bit Configuration of Slave Status (SSR) ................................................................ 494
Figure 14.4 Locked Address Configuration............................................................................... 495
Figure 14.5 IEBus Bit Format (Conceptual Diagram)............................................................... 496
Figure 14.6 Transmission Signal Format and Registers in Data Transfer ................................. 507
Figure 14.7 Relationship between Transmission Signal Format and Registers in IEBus
Data Reception ....................................................................................................... 510
Figure 14.8 Master Transmit Operation Timing........................................................................ 529
Figure 14.9 Slave Reception Operation Timing ........................................................................ 532
Figure 14.10 Error Occurrence in the Broadcast Reception (DEE = 1)....................................... 533
Figure 14.11 Master Receive Operation Timing ......................................................................... 536
Figure 14.12 Slave Transmit Operation Timing .......................................................................... 539
Figure 14.13 Relationships among Transfer Interrupt Sources ................................................... 540
Figure 14.14 Relationships among Receive Interrupt Sources .................................................... 540
Figure 14.15 Error Processing in Transfer................................................................................... 545
Section 15 Serial Communication Interface (SCI)
Figure 15.1 Block Diagram of SCI............................................................................................ 549
Figure 15.2 Block Diagram of SCI_0 of H8S/2239 Group ....................................................... 550
Figure 15.3 Example of the Internal Base Clock When the Average Transfer Rate
Is Selected (1)......................................................................................................... 583
Figure 15.4 Example of the Internal Base Clock When the Average Transfer Rate
Is Selected (2)......................................................................................................... 584
Figure 15.5 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits) ............................................................................................ 585
Figure 15.6 Receive Data Sampling Timing in Asynchronous Mode ....................................... 588
Figure 15.7 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)............................................................................................ 588
Figure 15.8 Sample SCI Initialization Flowchart ...................................................................... 589
Figure 15.9 Example of Operation in Transmission in Asynchronous Mode (Example with
8-Bit Data, Parity, One Stop Bit) ........................................................................... 590
Rev. 5.00 Aug 08, 2006 page lxxii of lxxxvi