H8S-2258 Datasheet, PDF (620/1071 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2200 Series

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
(c) Setting the IEBus Slave Address Setting Registers 1 and 2 (IESA1 and IESA2)
Specify the communications destination slave unit address.
(d) Setting the IEBus Master Control Register (IEMCR)
Select broadcast/normal communications, specify the number of retransfer counts at arbitration
loss, and specify the control bits.
(e) Setting the IEBus Receive Interrupt Enable Register (IEIER)
Enable the RxRDY (IERxI), RxS, RxF, and RxE (IERSI) interrupts.
The above registers can be specified in any order. (The register specification order does not affect
the IEB operation.)
(2) DTC Initialization
1. Set the start address of the RAM which stores the register information necessary for the DTC
transfer in the vector address (H'000004D2) to be accessed when a DTC transfer request is
generated.
2. Set the following data from the start address of the RAM.
 Transfer source address (SAR): Address (H'FFF80D) of the IEBus receive buffer register
(IERBR).
 Transfer destination address (DAR): Start address of the RAM which stores data to be
received from the data field.
 Transfer count (CRA): Maximum number of transfer bytes in one frame in the transfer
mode.
3. Set bit DTCEG6 in the DTC enabler register G (DTCERG), and enable the RxRDY interrupt
(IERxI).
Because the above settings are performed before frame reception, the length of data to be received
cannot be determined. Accordingly, the maximum number of transfer bytes in one frame is
specified as the DTC transfer count.
If the DTC is specified after reception starts, the above settings are performed in the receive start
detection (RxS) interrupt handling routine. In this case, the transfer count must be the same value
as the contents of the IEBus receive message length register (IERBFL).
Rev. 5.00 Aug 08, 2006 page 534 of 982
REJ09B0054-0500