M16C5LD Datasheet, PDF (63/85 Pages) Renesas Technology Corp – RENESAS MCU

M16C/5LD Group, M16C/56D Group
5. Electrical Characteristics
5.1.4 Flash Memory Electrical Characteristics
Table 5.5 CPU Clock When Operating Flash Memory (f_(BCLK))
V_CC = 2.7 to 5.5 V, at T_opr = -40 to 85°C unless otherwise specified.
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
-
CPU rewrite mode
10 ^{(1) MHz}
f_{(SLOW_R)}
-
Slow read mode
Low current consumption read mode
5 ⁽³⁾
fC(32.768) 35
MHz
kHz
-
Data flash read
2.7 V < V_CC ≤ 3.0 V
3.0 V < V_CC ≤ 5.5 V
16 ⁽²⁾
20 ⁽²⁾
MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). When using the 125 kHz on-chip oscillator clock or sub
clock as the CPU clock source, a wait is not necessary.
Table 5.6 Flash Memory (Program ROM 1, 2) Electrical Characteristics
V_CC = 2.7 to 5.5 V at T_opr = 0 to 60°C, unless otherwise specified.
Symbol
Parameter
Conditions
-
-
-
t_d(SR-SUS)
Program and erase cycles ^{(1, 3, 4) V}_CC ^{= 3.3 V, T}_opr ^{= 25°C}
Two words program time
V_CC = 3.3 V, T_opr = 25°C
Lock bit program time
V_CC = 3.3 V, T_opr = 25°C
Block erase time
V_CC = 3.3 V, T_opr = 25°C
Time delay from suspend request
until suspend
Min.
1,000 ⁽²⁾
Standard
Unit
Typ.
Max.
times
150
4000
μs
70
3000
μs
0.2
3.0
s
5 + CPU clock
× 3 cycles
ms
-
Interval from erase start/restart
until following suspend request
0
μs
-
Suspend interval necessary for
auto-erasure to complete ⁽⁷⁾
20
-
Time from suspend until erase
restart
-
Program, erase voltage
2.7
-
Read voltage
Topr= -40 to 85°C
2.7
-
Program, erase temperature
0
t_PS
Flash Memory Circuit Stabilization Wait Time
-
Data hold time ⁽⁶⁾
Ambient temperature = 55°C 20
ms
30 + CPU
clock × 1 cycle
μs
5.5
V
5.5
V
60
°C
50
μs
year
Notes:
1. Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n (n = 1,000),
each block can be erased n times. For example, if a 64 Kbyte block is erased after writing two word data 16,384 times, each to
a different address, this counts as one program and erase cycles. Data cannot be written to the same address more than once
without erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. It is advisable to
retain data on the erasure cycles of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
7. After an erase start or erase restart, if an interval of at least 20 ms is not set before the next suspend request, the erase
sequence cannot be completed.
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
Page 63 of 83