M16C5LD Datasheet, PDF (19/85 Pages) Renesas Technology Corp – RENESAS MCU

M16C/5LD Group, M16C/56D Group
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of thirteen
configure a register bank. There are two sets of register banks.
b31
R2
R3
b15
b8 b7
b0
R0H(high-order bitsof R0) R0L(low-order bitsof R0)
R1H(high-order bitsof R1) R1L(low-order bitsof R1)
R2
R3
A0
A1
FB
Data registers ⁽¹⁾
Address registers ⁽¹⁾
Frame base registers ⁽¹⁾
b19
b15
b0
INTBH
INTBL
INTBH is the 4 high-order bits of INTB register and
INTBL is the 16 low-order bits
b19
b0
PC
Interrupt table register
Program counter
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
Flag register
b15
IPL
b8 b7
b0
U I OB S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note:
1. These registers configure a register bank. There are two register banks.
Figure 2.1 Central Processing Unit Registers
REJ03B0307-0110 Rev.1.10 Dec 01, 2009
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